Development an efficient AXI-interconnect unit between set of customized peripheral devices and an implemented dual-core RISC-V processor

Abstract RISC-V set architecture is playing an increasingly important role in processor technology due to its open instructions which allow researchers build and improve computing systems. However, many architectures exist multi-core with complex designs, large area, high-power consumption. This paper studies open-source a simple design less power The depends on single core processor, Taiga. Two cores of Taiga are integrated chip while addressing issues related cache coherence, interconnect, memory design. A solution has been developed achieve data coherence between implemented caches the main memory; snoopy protocol. hardware-customized peripheral unit management process among operated cores’ tasks. For more consistent highly controlled storage, designed dual-port based specific protocol interface, 8192 lines word addressable unit. As UART common several devices processors for communication, as customized device appended communication other devices. System Verilog HDL extensively tested various testbenches ensure correct functionality. Hence, system performance evaluated using CoreMark benchmark, achieved 4.605 CoreMark/MHz Zedboard (FPGA Xilinx family) maximum operating frequency 98 MHz. results indicate that performs comparably state-of-the-art processors, offering simpler power-efficient Overall, research demonstrates potentialof creating processor.